FPGA-Based Software-Defined Radio (SDR) Development

The whole idea of software defined radio refers to shifting the signal processing from traditional hardware circuits to re-configurable digital platforms. The key technology that drives this transition is field programmable gate array (FPGA) because it offers reliable and high data processing capabilities, which host processor SDRs cannot deliver.

FPGA-based SP Devices, especially those combining RF transmitters with multi-processors SOCs, enable real-time operation of not only wideband communication systems, but also of radar and electronic warfare systems in compact design.

This article describes three instances of implementing FPGA-based Instant Signal Processing Devices ranging from peer-reviewed research to Government-subsidized defense projects.

Each case illustrates distinct architectural choices, performance outcomes, and lessons learned, collectively demonstrating the maturity and versatility of FPGA-based SDR technology across commercial, defense, and spectrum-sharing domains.

The ADRV9361-Z7035 platform integrates the Analog Devices AD9361 RF Agile Transceiver and the Xilinx Z7035 Zynq-7000 SoC to form a 2×2 MIMO RF front end that has the ARM processing system and programmable logic.

Because of a shortage of any successful implementations of OFDM systems found in the existing literature, the research team of the University of Oulu opted for this technology to develop the functional OFDM transceiver system.

The design methodology followed a disciplined hardware-software co-design flow. The team first created MATLAB models for each OFDM block, verifying behaviour through SDR MATLAB verification to avoid costly implementation errors.

These verified models were then translated into RTL implementations and deployed to the physical layer (PHY) of the ADRV9361-Z7035. A custom Linux kernel driver was developed at the medium access control (MAC) layer, providing local control over transceiving processes, direct memory access (DMA), and interrupt handling, while integrating TCP/IP functionality independent of MATLAB and Simulink.

The performance assessment through various modulation and coding schemes (BPSK, QPSK, and 16-QAM) and frequency ranges (UHF/VHF, ISM) yielded great results with the maximum throughput of 3.05 Mbps and spectral efficiency of 0.87 bps/Hz within 3.5 MHz, while the maximum transmitter power reached 13.6 dBm. The system performed best at 700-900 MHz.

Critically, the integrated system successfully supported real-time multimedia applications, including local video streaming at a 1.5 GHz downlink frequency and internet browsing, demonstrating end-to-end functionality beyond laboratory benchmarks.

An issue that has arisen and is constant in the development of SDR systems based on FPGA hardware is the impact of hardware-software co-design.

The Zynq architecture's programmable logic deals with deterministic baseband encoding, while its processor performs the protocol and higher layer processing, making for a useful division of tasks.

In defense applications where size, weight, power and cost (SWAP-C) are very important factors. FPGA-based software-defined radios have more advanced features compared to general-type microprocessors.

One of the companies from Princeton called BANC3, Inc. received a Phase II SBIR grant worth $1,099,404 from the Army to improve the technology for wideband RF sensing algorithms used for threat detection.

The architecture processes input RF signals simultaneously in both frequency and time domains in real time, generating spectra and pulse descriptor words that feed an intelligent data reduction technique.

Though the reduction decreases data throughput drastically, it can at the same time preserve the signal parameters' accuracy, which is a crucial factor for its embedding. In the course of Phase I, the algorithm correctly identified 76% of signals in complex signal environments having densities of up to 763 signals per second (ten variants of threat signals in total).

Under Phase II, the algorithm is being integrated onto an embedded ARM processor within a Direct RF FPGA, eliminating the need for external GPUs and making the solution suitable for SWaP-constrained platforms including drones, combat vehicles, and dismounted soldier systems.

The anticipated hardware-in-the-loop configuration targets 6.4 GHz of instantaneous bandwidth over an RF range of 100 MHz to 36 GHz, with key performance criteria including reaction time, latency, throughput, and threat signal recognition accuracy.

In this instance, it can be seen that the use of FPGA-based SDR systems allows for transferring the heavy process of signal classification from GPU clusters in laboratories onto the platforms intended for use in the field. Besides, the use of signal templates created via modeling and real-world data demonstrates the usefulness of the method being applied.

The third case shifts focus to spectrum sharing, a critical challenge as 5G and future 6G systems compete for limited RF spectrum.

Researchers at the University of Strathclyde developed a reconfigurable wideband spectrum-sensing platform within the ON-SIDE project, implemented on an AMD Zynq UltraScale+ RFSoC 670 DFE device.

The system operates in the UK within the 3.8–4.2 GHz band (n77), capable of acquiring a maximum bandwidth of 400 MHz while tuning across a bandwidth range of 0 to 4.9 GHz.

The device uses a processing pipeline with a complex channelizer and energy detector constructed on the FPGA platform, which enables the operation of 106 channels in parallel, making it possible to monitor energy in real time with a channel resolution of 3.84 MHz, which corresponds to the smallest OFDM sub-carrier spacing in 5G NR.

An embedded PYNQ-based control dashboard allows configuration and live visualisation, while a Python ZeroMQ publisher-subscriber framework distributes sensing data to multiple remote clients.

Field tests involving the live 5G NR signals within the n77 and n78 bands have determined accurate, low-latency energy detection and remote operation. This means that the device is a highly effective basis for cognitive radio and dynamic spectrum management, as it provides the necessary hardware.

The deployment reveals yet another benefit of the RFSoC system, as the direct RF sampling means that the analog down-conversion phase is not needed, simplifying the process and allowing for the broad bandwidth needed for efficient spectrum monitoring.

There are many frameworks and techniques visible in all three implementations. In the first place, we would like to note that the function of hardware-software separation is of paramount importance.

The Zynq and RFSoC families represent systems that allow designers to reserve deterministic signal processing features to programmable logic while using the processing unit for control, communication, and processing on higher levels. This essential separation enables the fulfillment of real-time deadlines not achievable with host-processor architectures.

In addition, resource utilization and performance characterise the essential trade-off that exists in this context.

A recent feasibility study in which a Chessboard-based automatic modulation classification algorithm was implemented on an RFSoC FPGA revealed that the parallel design using all the necessary peripherals produced a throughput speed of 29.0 GBps while utilizing 82.31% of the lookup tables and 50.67% of the flip-flops, while the datapath-only design produced a throughput index of 24.8 GBps while consuming much smaller resources altogether.

As parallel instances increase, bandwidth growth saturates and maximum operating frequency decreases—a constraint that designers must navigate through careful architecture selection.

Thirdly, open-source frameworks help speed up the process of development. This is evident in developments with the PYNQ framework where there have been numerous gains in lowering the cost of developing SDR systems using FPGAs.

The Pluto-PYNQ project showcases that even cheap and simple platforms using Xilinx Zynq-7000 SoCs can serve as really useful and educational SDR platforms for creating and showcasing DSP functions on real radio signals.

Fourthly, deterministic latency continues to be a significant obstacle. The Integrive-100 platform, which makes use of the AD9361 SDR, is equipped with an already constructed FPGA PHY baseline and aims to solve the question of the non-deterministic latency of real-time signal processing brought about by the dependence on the host PC.

By offloading real-time signal processing entirely to the FPGA and integrating an ARM processor with Embedded Linux, such platforms eliminate host-induced jitter while retaining compatibility with existing SDR software stacks.

FPGA-based software-defined radio processing platforms have matured from research curiosities to production-grade systems spanning commercial communications, defense electronic warfare, and dynamic spectrum access.

The three examples described in this paper - a real-time OFDM transceiver working at 3.05 Mbps over a bandwidth of 3.5 MHz, a defense RF sensing system operating at 6.4 GHz instantaneous bandwidth and based on FPGA technology, and a 5G spectrum sensing system working at a 400 MHz bandwidth and supporting 106 parallel channels - show that the technology can bring real value in different applications.

The achievement in this area less relies on FPGA capability than on a disciplined co-design process by dividing algorithms functionality between programmed logic and processing units, designing architectures to find the balance between bandwidth and resources needed, and utilizing open platforms like PYNQ to minimize integration costs.

In light of the fact that wireless systems are evolving to operate at higher frequency, provide wider bandwidth, and employ more flexible spectrum sharing methods, the importance of FPGA-based SDR infrastructure is never easier to overestimate.