ARM-Based Custom SoC FPGA Prototyping & Development Services | Case Study

This case study examines the design, implementation, and validation of FPGA prototypes for ARM-based custom System-on-Chip (SoC) designs.

In this article, we are going to analyze three relevant projects: From low-cost Cortex M0 based SoC on low-cost FPGA Basys 3, development of Cortex-M3 based IoT subsystem prototype on Xilinx Arty100-T platform, and large-scale emulation of ARM v8 based dual-core processors on multi-FPGA Virtex VU19P platform.

All the cases indicate the possible variety in FPGA prototyping, starting from the prototype designed for educational and research purposes ending up with production-grade pre-silicon validation.

During the research, architectural trade-offs are examined, bus interconnects are customized, hardware-software co-design is used, and practical knowledge is gained after the migration from simulation to hardware.

The above technologies have provided each project with reliable functional validation on real silicon thus proving that FPGA prototyping is the effective way of proving the viability of any ARM-based SoC design before moving to ASIC fabrication.

1.1 The Role of FPGA Prototyping in SoC Development

FPGA-based prototyping is the process of debugging, verifying, and validating part or all of a system on one or more adaptive SoCs or FPGAs.

In case of ARM-based custom SoC designs, prototyping serves two different functions: first, it allows for hardware-software co-validation prior to the availability of physical silicon and, secondly, it provides a realistic platform for the execution of firmware, operating systems and application software alike.

An industry expert suggested that high-speed execution of SoC models on FPGA-based prototyping systems is an essential capability for development and validation of the entire software stack, as well as for understanding hardware/software interactions.

1.2 Why ARM Cores for Custom SoCs?

Due to their efficiency in performance-per-watt, wide ecosystem, and availability of synthesizable IP through programs such as ARM DesignStart, ARM processors have become the market leader in embedded and mobile computing.

The Cortex-M family is designed for microcontroller applications, while the Cortex-A family is suitable for application workloads.

FPGA (field-programmable gate array) prototyping is a highly valuable process that allows designers to implement an ARM processor core in programmable logic, link it with custom peripherals using AMBA bus architecture, and validate the complete system at virtually real silicon speeds.

2.1 Project Description

Causality SoC is located at the educational and research pole of the spectrum of FPGA prototyping projects. Created using a Digilent Basys 3 development board and programming in Verilog HDL, this system incorporates the official ARM Cortex-M0 DesignStart IP core together with a wide range of peripherals and a software stack.

The aim of the work was to create a flexible and easy-to-use SoC that can be easily adapted for different applications, as developers can expand the functionality by connecting new peripherals written in Verilog or VHDL and implementing appropriate drivers.

2.2 Architecture and Bus Interconnect

The SoC uses the AMBA 3.0 AHB-Lite bus protocol, a memory-mapped interconnect with an address decoder and bus multiplexer.

The Cortex-M0 processor core includes the complete Nested Vectored Interrupt Controller (NVIC), enabling interrupt-driven real-time programming. The peripheral set includes a VGA controller, UART, timer, GPIO, 7-segment display, and block RAM, all connected through the AHB bus fabric.

2.3 Software Stack and Demonstration Application

This project consists of a complete software stack, which includes ARM CMSIS (Cortex Microcontroller Software Interface Standard) along with a custom-built Hardware Abstraction Layer (HAL) plus some interrupt service routines.

A decentralized Snake game was initially developed by the project maker to validate the whole system, involving real-time graphic rendering on a VGA display, keyboard and serial input through UART, and game state control using interrupts.

2.4 Lessons Learned

DesignStart helps you get started.

With the availability of Cortex-M0 on ARM's DesignStart portal, designing and prototyping SoC based on Cortex-M0 is much easier because expensive IP licenses are not required anymore.

HAL makes application development take place faster.

Creating an abstract hardware layer on top of SoC simplifies the process of creating applications without requiring in-depth knowledge of the bus architecture.

Educational prototyping builds foundational expertise.

This project demonstrates that FPGA prototyping is not limited to industrial-scale designs; even low-cost platforms can serve as effective vehicles for developing and demonstrating complete SoC functionality on real over-the-air signals.

3.1 Overview of the Project

A customized IoT subsystem and peripherals with an ARM Cortex-M3 processor was developed in this project, which is suitable for embedded IoT applications.

This project was designed to meet specific requirements and specifications of the application. Validation of the chip functionality was carried out on the Xilinx FPGA after implementation on the Intel FPGA platform.

3.2 Bus Interconnect Customization

In its original design, the Cortex-M3 had only a handful of slave and master interfaces for interfacing peripherals. However, through customization, it was possible to increase the number of master and slave ports. This was done by manipulating the AHB and APB interconnects and changing the port mapping of the various ports using address decoding logic.

To make all these changes, it was necessary to study the AMBA protocol closely to ensure compliance with the protocol in spite of the large number of peripheral masters that were added.

3.3 Implementation and Verification Flow

The development flow used Keil uVision5 software to translate C programs into binary files loaded into the SoC's memory for the processor to run, while Xilinx Vivado was used for simulation. Hardware implementation on the Arty100-T FPGA platform validated the modified Cortex-M3 design against the test cases.

3.4 Results and Lessons Learned

It is not easy to modify the bus interconnect

The expansion of the AHB/APB interconnect necessitated addressing logic and memory mapping alterations. The success of the project served as an illustration of the fact that even minor interconnect modifications require thorough verification.

Cross-platform portability validates design robustness.

The migration from Intel FPGA to Xilinx FPGA provided an additional layer of validation, confirming that the design was not dependent on vendor-specific primitives.

Hardware implementation catches simulation escapes.

FPGA prototyping validated the test cases again for the modified Cortex-M3 design, uncovering issues that simulation alone did not expose.

4.1 Project Overview

Towards the apex of prototyping continuum, a US-based semiconductor manufacturer reached out to Ignitarium's semiconductor team for developing a FPGA emulation environment for an ARM-based server-grade processor on a Xilinx Virtex VU19P FPGA.

The project encompassed complete ownership of the FPGA emulation project, including the FPGA migration development effort of an ARMv8-based dual-core processor SoC, FPGA migration and testing of the secure power management, and DDR4 interfacing.

4.2 Architectural Partitioning and Multi-FPGA Implementation

The complexity of the design exceeded the capacity of a single FPGA, requiring partitioning across two different FPGAs on an S2C platform.

A Time Division Multiplexing (TDM) design was implemented for data transfer across FPGAs due to I/O pin limitations, with an auto-calibration logic ensuring proper sampling of data on the receiver board. Utilization exceeded 80% on both FPGAs, pushing the devices to their practical limits.

4.3 Starting Up and Testing of Software

The launch of the hardware was performed using two VU19P logic systems and connections to external devices. Modules such as I2C, UART and DDR4 were tested through JTAG and OpenOCD. The Linux operating system was installed and standard applications were executed on the FPGA system to achieve full software compatibility.

4.4 Results and Corporate Influence

The project established an acceleration platform for the client towards future emulation initiatives. The reused infrastructure was aimed at pre-silicon verification. The successful integration of the Linux OS showed that the ARMv8 cores work properly in the built-up FPGA environment.

4.5 Lessons Learned

The partitioning process is one of the biggest technical challenges.

The division of complex SoCs across many FPGAs requires considering the bandwidth, latency, and signal integrity across different devices. The use of TDM has resolved the bottleneck experienced with I/O; however, it has also resulted in the complexity of synchronization.

Auto-calibration is essential for multi-FPGA links.

Without automatic calibration logic, the data sampling on the receiver board would be unreliable, especially across temperature and voltage variations.

Software bring-up validates the hardware.

Running Linux and standard applications on the emulated processors provides the strongest possible evidence that the hardware design is functionally correct.

5.1 The Prototyping Spectrum.

The three projects represent the full spectrum of prototyping. The Cortex-M0 project reveals how low-cost platforms and free IP can achieve valuable SoCs prototyping. The Cortex-M3 project demonstrates how bus interconnection customization can be used for application optimization. The ARMv8 emulation project shows that multi-FPGA platforms are effective in the validation of complex server-class processors.

5.2 The Need For Co-Designing Hardware And Software

In all schemes hardware-software co-design has proven to be necessary. In particular, the ability to execute real software on the prototype has helped check the functioning of not only the engine itself but also of the whole system altogether.

5.3 Bus Architecture Choices Drive System Capability

The AHB-Lite bus in the Cortex-M0 design provided a simple, low-gate-count interconnect suitable for microcontroller-class systems.

The expanded AHB/APB interconnect in the Cortex-M3 design accommodated additional peripheral masters.

The multi-FPGA ARMv8 design required TDM-based interconnect across device boundaries. The choice of bus architecture directly determines the scalability and performance ceiling of the prototype.

5.4 Validation Should Involve Hardware

Only using simulation is inadequate as far as SoC validation is concerned. In the case of the Cortex-M3 project, for example, FPGA prototyping was employed for the purpose of validating the various test cases with the help of the modified design. The ARMv8 project, in turn, had to use the hardware bring-up approach and JTAG and OpenOCD for the purpose of verifying the operation of the unit.

FPGA prototyping for ARM-based custom SoCs has matured into a disciplined engineering practice spanning educational, research, and production-grade applications.

The three applications analyzed here – a Cortex-M0-based system-on-chip (SoC) implemented on a Basys 3 field-programmable gate array (FPGA), a customized Cortex-M3 Internet of Things (IoT) system on a Xilinx Arty100-T FPGA with a scalable Advanced High-Performance Bus (AHB)/Advanced Peripheral Bus (APB) protocol, and an AMP Linux-compatible ARMv8 dual-core processor model on a multi-FPGA Virtex VU19P—confirm that FPGA prototyping allows obtaining tangible results.

Success in this area hinges upon the adoption of disciplined co-design by choosing appropriate processing core and bus architecture for the application, distributing the design across FPGA resources, and verifying the whole hardware-software stack on real silicon.

As SoC complexity increases, the need to accelerate time-to-market will ensure that FPGA prototyping continues to play an important role in the ARM-based SoC development process.