What Functional Safety Means for STM32 Firmware

Consider an electrically powered machine with a safety door that will stop any movement in a risky operation upon the opening of the door, and thus preventing the machine from restarting inadvertently.

It must also be programmed to read validated data, initiate an output action, identify any malfunction signal, and report to the user.

The machine must make it possible to reach the safe condition needed for safety operation of the machine regardless of the failure of the processor.

IEC 61508 provides the general framework for electrical, electronic, and programmable electronic safety-related systems. Machinery projects may use IEC 62061 or ISO 13849-1:2023; process-industry safety instrumented systems are addressed by IEC 61511.

The applicable standard, required risk reduction, and scope of independent assessment are established for the particular product and application. A safety function can span several devices, so firmware cannot be evaluated in isolation.

Relevant Adequate Infosoft Project Experience

These examples show experiences in STM32, controlling, sensing, and fault management. It should be noted that these examples cannot qualify as independently certified safety products. During the initiation of any new safety project, we agree on the requisite standard to follow, responsibilities of the customer, necessary proofs, and the intervention of the assessor.

Start with the Hazard and Safety Requirement

The first step in the process is to establish the project objective and the foreseeable defects and hazardous consequences, and determine the responsibilities of all subsystems.

A good safety requirement indicates what triggers the response, maximal response time, the acceptable output state, and how to reset the system. A requirement like "detect errors quickly" is not specific enough in terms of utilization in the design/testing process.

The requirement is traced back to the architecture, program code, tests, and results. In case the sensor debounce time changes, the reviewers can see which response time requirement was triggered.

The interfaces with non-safety software must be rigorously delineated, so a loss of connection should never disable the local safety feature.

The safety manager determines the required SIL (Safety Integrity Level) or PL (Performance Level) and the evidence expected. It is important to note that marketing claims cannot replace hazard analysis, calculations, or the assessor's decision.

STM32 Architecture and X-CUBE-STL Integration

ST presents a functional safety package known as X-CUBE-STL that is designed for certain STM32 devices. Included in this package are such documents as safety manual for microcontroller (MCU), failure analysis documents, and self-test libraries dealing with CPU as well as SRAM and flash memories.

However, these documents may help to support a safety case when the condition of their use correspond to the device and architecture type. According to ST, one STM32 microcontroller can be used in relation to certain SIL2 safety functions as it is one STM32 used for SIL3 functions that comprises two STM32s working in 1-out-of-2 mode.

This is architecture guidance, and not a guarantee of compliance with SIL2 or SIL3 standards for a specific product.

We select an MCU against memory, I/O, diagnostic, environmental, and safety-manual requirements. The design considers clock monitoring, watchdogs, memory tests, sensor disagreement, output feedback, and periodic checks. Every test needs a detection latency and defined reaction. A diagnostic that leaves an actuator energized has not finished the safety job.

X-CUBE-STL integration must respect timing, memory placement, the selected toolchain, and the application's scheduling model. We document the library version and device-specific assumptions, measure worst-case execution time, and test fault reactions on actual hardware.

We also identify faults that MCU self-tests cannot detect, such as a welded relay, failed transducer, or broken wire. Those require system-level measures and verification.

Firmware Services Across the Safety Lifecycle

Safety-oriented architecture

We ascertain the boundaries of the task, priorities for interruption, sequence of startup actions, transitions that guarantee safety, independent supervision, and the connection between safety and comfort features.

We ascertain the boundaries of the task, priorities for interruption, sequence of startup actions, transitions that guarantee safety, independent supervision, and the connection between safety and comfort features.

In the case of a necessity for certified or any other qualified software components, we examine its adoption and usage as per the assurance scheme of the project and not according to its brand.

Defensive embedded implementation

We implement bounded inputs, explicit state machines, controlled memory use, error handling, and observable fault reporting. The code distinguishes a process alarm from an internal diagnostic failure.

We implement bounded inputs, explicit state machines, controlled memory use, error handling, and observable fault reporting. The code distinguishes a process alarm from an internal diagnostic failure.

Clearing an alarm should not automatically re-energize machinery; restart conditions are specified separately and tested.

Diagnostic coverage and fault response

We will implement self-tests, watchdog monitoring, evidence checks, output checks, and timeout procedures to mitigate occurred fault conditions.

We will implement self-tests, watchdog monitoring, evidence checks, output checks, and timeout procedures to mitigate occurred fault conditions.

Time plays a critical role here: a RAM self-test upon the system boot-up will not cover faults emerging during the operation. The diagnostic claims should be based on failure modalities, reaction time, and evidence.

Verification and traceability

We will analyze requirements and software code, carry out the unit and integration testing, simulate faults, and get the results on the target hardware.

We will analyze requirements and software code, carry out the unit and integration testing, simulate faults, and get the results on the target hardware.

We will capture the software build, testing, simulation, output from the system, and passing criteria.

Release and maintenance

We establish configuration control, reproducible builds, change-impact review, and a firmware update and recovery strategy. An update that interrupts the device must not leave an unsafe output state.

We establish configuration control, reproducible builds, change-impact review, and a firmware update and recovery strategy. An update that interrupts the device must not leave an unsafe output state.

Field diagnostics should identify a fault without encouraging an operator to bypass the protection to resume production.

Testing the Failures That Matter

The verification plan begins with what is required to happen, when it should occur, and how it will happen. The various tests include disconnected inputs, impossible sensor readings, processor resets, blocked tasks, voltage drops, update interruptions, and communication errors.

The distance from the fault limit to output measured is also considered.

Fault injection is not without its limitations. Changing the value of a software variable does not mean that there is also a corresponding physical sensor failure and does not confirm that the program is capable of detecting random system failures.

Bench tests, hardware-in-the-loop exercises, and installation validation serve different purposes. An acceptance report should state what was tested, what remains outside scope, and which assumptions require confirmation by the system integrator.

Safety and cybersecurity also interact. Remote configuration, network commands, and firmware updates can affect safety behavior.

We define who can change setpoints, how changes are validated and logged, and what the controller does when a command is stale or unauthenticated. Cybersecurity controls support the safety design, but an authenticated network request is not by itself a safe operating condition.

Deliverables That a Reviewer Can Inspect

The expected deliverables include the firmware requirement specifications, system architecture, interfaces, source code, building process, traceability information, diagnostic reports, testing procedures, failure injection results, and release documentation.

We usually keep track of any assumptions made regarding the sensors and actuators, electricity supply, maintenance, and conditions of operation. With some assumptions missing, the tested firmware cannot be validated.

For the old STM32 controller, instead of just relabeling existing code as SIL-compliant, we should start with the gap analysis of all available information regarding requirements, hardware failure paths, libraries used, and some tests conducted before.

The main objective of the gap analysis is the identification of the things that can be kept, redesigned, or need approval from the certification authority.

Frequently Asked Questions

Does the usage of X-CUBE-STL guarantee the safety of my STM32 device?

No. The package provides information such as details on the device and diagnostic capabilities, but does not cover the entire range of safety evaluation actions needed to certify a device according to relevant standards.

Can a watchdog alone make firmware functionally safe?

No. It can detect some stalls, but cannot diagnose every sensor, logic, memory, or output failure. Its timeout and the hardware reaction after a reset must also meet the safety requirement.

Do all industrial systems need SIL3?

No. The required risk reduction follows the hazard assessment and applicable standard. Selecting a higher rating without a defined safety function does not resolve the engineering problem.

What information is required for the proper assessment scoping?

Provide system diagram, hazards and risk analysis, safety functions that will be provided by the product, STM32 part number, input/output circuits, timing constraints, and the target market of the project. The details will allow us to define firmware development scope.

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Ashok Patel
Ashok Patel
Senior Engineering Project Manager
AI/ML, DevOps, Data Science & Automation | IoT & C#/.NET | Azure & AWS Expert | Certified AI & Cloud Engineer | 1,500+ LinkedIn Followers