Resonant DC-DC Converter Development Using TI C2000™ F280039C

Client: A European manufacturer of industrial power supplies

Challenge: Design and manufacture a 400V-to-12V High Efficiency DC-DC converter with good load transient characteristics for Telecom infrastructure.

Solution: Design and prototype a custom PCB with TI C2000(F280039C) Real-Time

Outcome: A fully functional 1kW prototype achieving a peak efficiency of 96% and a load transient recovery of <50µs, a 60% improvement over the previous generation—delivered within a 14-week development cycle.

The client required a power supply that could handle rapid load fluctuations (from 10% to 100% load in microseconds) without significant voltage droop or overshoot. Traditional LLC (Inductor-Inductor-Capacitor) resonant converters using analog controllers struggled with this requirement.

We selected the TMS320F280039C from the TI C2000™ real-time MCU family for three critical reasons :

Real-time processing:

High-performance 32-bit C28x DSP core with floating-point unit (FPU) provides processing capability at a rate of 240 MIPS to support on-the-fly computations of complex control laws.

HHC:

The flexibility of our MCU allowed the implementation of hybrid-hysteretic control (HHC), a new control algorithm that combines direct frequency control (DFC) and an inner charge control loop. HHC provides much better load transient performance than conventional voltage or current mode control methods.

HRPWM:

The 150ps resolution of the PWM modules enabled precise frequency control of the resonant tank; this was essential to achieve zero-voltage switching (ZVS) over a wide range of output loads.

The layout of high-frequency power conversion boards must be done in a very precise manner. We used TI's C2000 hardware design guidelines for designing mixed-signal systems and applied these guidelines specifically to design the gate drive circuitry and current-sense circuits of the system.

A. Layer Stackup for Noise Isolation and Thermal Management

To reduce mains- and switching-noise coupling between the primary (400V) side of the PCB and the secondary (12V) side, we created a 4-layer stackup for this design.

• Top Layer (Power):

  High-current traces for the primary half-bridge MOSFETs and secondary synchronous rectifiers.

• Inner Layer 1 (Ground – Primary):

  A dedicated return path for the primary side control logic.

• Inner Layer 2 (Ground – Secondary):

  Isolated ground for the 12V output.

• Bottom Layer (Control):

  F280039C microcontroller (on a dedicated controlCARD interface), analog feedback networks, and communication lines.

B. Mitigating Gate Drive Noise

The switching node (half-bridge midpoint) experiences high dV/dt (up to 50V/ns). To prevent this noise from corrupting the MCU's ADC readings:

• Kelvin Connections:

  The low-side current shunt resistor (used for inductor current sensing in HHC) was routed with a Kelvin connection directly to the F280039C's internal programmable gain amplifier (PGA). This eliminated voltage drops caused by high-frequency currents in the ground plane.

• Layout Separation:

  We physically isolated the gate drive traces (from the LMG3422 GaN half-bridge EVM interface) from the low-voltage analog feedback traces by at least 5mm, crossing them at 90-degree angles only.

C. Analog Front-End Design

The F280039C has a 12-bit, 3.45 MSPS ADC with an integrated PGA that we used to amplify the shunt resistor's current sense voltage. The integrated PGA eliminates the need to use an external operational amplifier, thereby saving substantial PCB real estate as well as reducing the Bill of Materials (BoM) cost by approximately 15%.

Challenge 1: ADC Noise at Light Load

During initial testing, the output voltage ripple was acceptable at full load (1kW) but became noisy (<100W). The issue was traced to discontinuous conduction mode (DCM) causing high-frequency ringing that coupled into the ADC reference pin.

Solution:

The source of the problem was determined to be high-frequency ringing caused by Discontinuous Conduction Mode (DCM) that coupled into an ADC reference pin.

To mitigate this issue, we moved the VDDA (analog power) decoupling capacitors (0.1µF and 4.7µF) to within 2mm of the associated MCU pin and provided a dedicated via for connecting the decoupling capacitors directly to the Analog ground plane.

In addition, we enabled the ADC's built-in hardware oversampling filter, which allowed the averaging of 8 samples and elimination of noise at output voltage levels near or below 100 Watts.

Challenge 2: Implementing HHC in Software

The HHC algorithm requires computing the charge delivered to the resonant tank each switching cycle and comparing it with an internal ramp. This is computationally intensive.

Solution:

We utilized the C2000's Control Law Accelerator (CLA) — an independent 32-bit floating-point co-processor. The CLA handled the inner charge control loop while the main C28x CPU managed communications (UART, CAN-FD) and the outer voltage loop. This parallel processing achieved the sub-100ns latency required for stable HHC operation.

Challenge 3: Thermal Management

The F280039C itself runs cool, but the surrounding GaN FETs (handling 4kW peaks) generate significant heat.

Resolution:

The PCB was designed with 12 thermal vias under the MCU's ground pad (if using QFN package) and a continuous copper pour on the bottom layer to sink heat away from the voltage regulator module (TPS650352-Q1 PMIC) powering the C2000.

Hardware Validation

We utilized the TMDSCNCD280039C controlCARD—a standardized evaluation module containing the F280039C. This plugged into a custom-designed power stage board via an HSEC180 connector. This modular approach allowed us to validate the power stage separately from the MCU firmware.

Software Bring-up

Using TI Code Composer Studio (CCS) and the DigitalPower SDK, we imported the pre-validated HHC library for the LLC converter.

• SysConfig Tool:

  Used to configure the ePWM modules to generate the 200kHz variable-frequency drive signals with 150ps resolution.

• SFRA (Software Frequency Response Analyzer):

  Injected a small perturbation into the voltage control loop while measuring the output. This allowed us to tune the PID coefficients of the compensator without a network analyzer, reducing tuning time by 50%.

• C2000 Academy:

  The team utilized TI's free online training modules to understand the nuances of the CLB (Configurable Logic Block) to generate custom interlocking for the synchronous rectifier FETs.

The final prototype underwent rigorous validation:

Efficiency:

Achieved 96% peak efficiency @ 800W dropping to 94% @ 1kW; only limited by the transformer copper losses as opposed to controller functionalities.

Load Transient:

When switching load from 100mA to 10A (1%-10%), output voltage went down 120mV, settling within 40µs, which is well within the telecommunications specifications of 250mV/200µs.

Thermal Performance:

The F280039C operated at ambient temperature (25°C); therefore, no external heatsink is required due to the 90nm low-loss design and the use of appropriate PCB thermal relief.

This case study demonstrates that the TI C2000 series is the gold standard for real-time power control. Unlike standard MCUs, the F280039C provided the unique combination of a DSP core for math, a CLA for parallel processing, and HRPWM for precision timing.

Key Takeaways for Engineers:

• Leverage Integrated PGAs:

  For current sense, use the C2000's internal PGAs to save board space and reduce offset errors.

• Use controlCARD for Prototyping:

  The standardized card format allows you to debug power electronics without risking a custom MCU board.

• Utilize the CLA:

  Offloading control loops to the CLA prevents main CPU interrupts from causing instability.

• DigitalPower SDK is Essential:

  Do not write code from scratch, use TI's optimized, pre-tested library functions for topologies like LLC and Totem-Pole PFC.

By following TI's reference designs (like TIDA-010092 for motor control or PMP40690 for PFC) and adapting them, we delivered a robust, production-ready digital power supply ahead of schedule.