FPGA-Based Motor Control and Encoder Processing System Development

Knowledge and Reliability. It was essential to have a four-axis servo platform with a current-loop bandwidth of at least 5 kHz per axis and a deterministic jitter smaller than 100 ns.

Also, the platform had to support incremental and absolute encoders. In the evaluation, three platforms were considered against the requirements.

Platform	Strengths	Disqualifying or Costly Factor
ARM Cortex-M7 MCU (STM32H7)	Low cost, mature toolchain, integrated ADC	Fixed architecture; sequential execution limits multi-axis current-loop concurrency; jitter in the tens of microseconds under interrupt load
Dual-core DSP (TMS320F28379D)	Fast math, integrated PWM and ADC	Fixed peripherals; limited flexibility for non-standard encoder protocols; multi-axis scaling requires multiple devices
FPGA (Xilinx Artix-7 XC7A35T)	True parallel execution of four independent current loops; deterministic nanosecond timing; reconfigurable I/O for any encoder protocol	Higher development effort; requires HDL expertise; no integrated analog front-end

The FPGA device was chosen because research shows that from the point of view of parallel processing, high-speed operation, and low latency, it surpasses microcontrollers (MCUs) and digital signal processors (DSPs) and thus is suitable for use in advanced real-time control systems.

Furthermore, there was one more advantage specific to this project - unlike other designs offered by other vendors, the system is capable of multi-axis scaling without decreasing its working parameters.

Specifically, since each section of the FOC pipeline is implemented in separate hardware, in order to add the fifth axis only the logic resources of the FPGA chip have to be expanded, while the interval between the control outputs remains unchanged.

Of course, this approach has its particularities: it required a hardware engineer knowledgeable about Verilog programming, and also it is required more time for implementation of the project.

Specialization. The approach was broken down into three classifications: the FPGA structure, the analog starting position as well as the host processor.

The FPGA has an Artix-7 XC7A35T with 33,280 logic cells, 1,800 Kb of block RAM and 90 DSP48E1 blocks, that housed four independent controlled flux pipelines, four coding-decoding modules, four SVPWM generators and a shared security module.

The analog front-end included four blocks of three-phase inverters, each with low-side shunt current measurement and an actuator with hardware desaturation identification.

The host processor (an ARM Cortex-A7 operating with Linux) uses an AXI4-Lite register interface to communicate with the FPGA for data transfer and command execution.

Published work on FPGA-based PMSM control systems confirms this architecture: a Cyclone IV FPGA was used with a four-layer PCB integrating power regulation, AD sampling, and encoder reception, with Verilog HDL implementing the core control logic and experimental validation via SignalTap and oscilloscopes.

The present design followed the same philosophy but scaled the control logic to four independent axes.

3.1 Incremental Quadrature Decoding

Expertise. The incremental encoder interface was implemented as a dedicated Verilog module that performed synchronization, debouncing, direction detection, and position counting in hardware.

The synchronization stage used a two-flip-flop synchronizer clocked at 100 MHz to eliminate metastability from asynchronous encoder inputs. Debouncing was implemented with a configurable counter: the input was considered stable only after the debounce counter reached a programmable threshold, which was set to 5,000 clock cycles (50 µs at 100 MHz) — longer than the encoder's worst-case transition time but shorter than the shortest expected signal-hold time at maximum speed.

The quadrature state transition table helped establish direction and position. The logic used to define direction was as follows: direction = a_new XOR b_prev.

The counter can take different sizes using a Verilog generic parameter so that it can be reused for all encoders irrespective of their resolution.

The output of the position will be latched into a register that can be accessed both by the internal FPGA FOC and the host processor via AXI.

According to a published approach to encoder-based FOC for PMSM motors, it is stated that a new algorithm was found which allows to determine the direction of the rotation within a quarter of the encoder resolution in connection with reliable interpretation of its quadrature signals (A, B and Z).

The approach described in this design used a similar method of determining the direction with quarter resolution, where the Z-index pulse initiates the absolute zero reference at the rise of the power supply.

3.2 Absolute Encoder Protocols (BiSS and SSI)

In terms of technical knowledge, the FPGA's BiSS-C master interface was developed by utilizing Verilog for accurate feedback through position. BiSS (Bidirectional Serial) is a serial protocol that makes use of two differential signals for the transfer of information (the MA clock and the data SLO).

The master circuit generates the clock signal while the encoder transmits the position, status information, and CRC.

Various techniques were used in the development of the FPGA module that utilized finite-state machine technology for producing programmable clock frequency of 1–10 MHz, receiving the data from the encoder on the falling edge, and verifying the CRC to enable transferring of the position information to the control pipeline.

Since BiSS-C is compatible with SSI, it's possible to use the same physical layer for both SSI and BiSS, thus allowing the platform to accommodate both encoder types without changing any hardware.

This has been confirmed in literature. The BiSS standard is hardware-compatible with SSI, and the users can operate SSI-compatible encoders on the same interface.

The downside is that SSI does not provide the bidirectional register access that BiSS offers, which means that BiSS features like accessing the parameters of the encoder on the encoder side are not possible in the SSI mode. Unfortunately, this shortcoming has been noted instead of being hidden.

3.3 Resolver-to-Digital Conversion (Optional Path)

The platform reserved a resolver interface for applications requiring absolute position in harsh environments.

The resolver-to-digital conversion was implemented as an open-loop tracking loop in the FPGA: the resolver's sine and cosine outputs were sampled by external ADCs, demodulated synchronously with the excitation reference, and fed to a Type-II tracking loop that estimated rotor angle and speed.

Research shows a new R/D converter that uses synchronous detectors to demodulate signals, A/D converters to convert analog signals to digital signals, and a built-in look-up table to convert angular data that is implemented on FPGA and can be configured to any resolver.

In the present design, this architecture was followed, but resolver interface was not included in the first build; that design leaves FPGA logic and footprint for future updates instead of claiming it as missing feature.

4.1 FOC Algorithm Partitioning

Expertise. Each axis's FOC pipeline was implemented as a pipelined hardware module operating at 20 kHz (50 µs period). The pipeline stages were:

• Clarke transform - converts three-phase currents Ia, Ib, Ic to stationary-frame Iα, Iβ.
• Park transform - rotates Iα, Iβ to the rotor frame Id, Iq using the encoder angle.
• PI controllers - independent PI regulators for Id (flux) and Iq (torque), with anti-windup clamping.
• Inverse Park transform - rotates the voltage commands back to the stationary frame.
• Space-vector PWM (SVPWM) - generates the three-phase duty cycles.

The entire pipeline was fully pipelined, meaning a new current sample entered the pipeline every 50 µs and a new PWM duty cycle emerged 10 clock cycles (100 ns) later. This latency is two to three orders of magnitude lower than an equivalent sequential MCU implementation, where the FOC algorithm alone can consume 5–20 µs of CPU time per axis per cycle.

4.2 Hardware Parallelism and Multi-Axis Scaling

Expertise. The four FOC pipelines were run at the same time, and they are all different hydrogenation systems using the FOC method which has its own programming module, state, and control mechanism.

Since all pipelines are completely separate pipelines, none of them has struggled.

The patent application for the FPGA-based motion control notes that with entirely hardware-implemented current loop, only a few dozen microseconds are required to perform all control algorithms in current loop, thus minimizing the control time and increasing the bandwidth of current loop.

The present design achieved a 50 µs control period with four axes in parallel, which would be impractical on a single sequential processor without significant performance compromise.

A published FPGA-based high-speed PMSM control system using a current-speed dual-closed-loop structure and SVPWM modulation confirms the feasibility of this approach, reporting system stability and good driving performance validated by SignalTap and oscilloscope measurements.

4.3 PI Controller Implementation

Implementation procedures. The PI controllers in this system were implemented as DSP48E1 slices, which carry out 25-bit operations. Information generating two variables in the proportional part was implemented in the firmware by performing multiplication in fixed-point arithmetic. The integral controller was realized using a saturating accumulator and a back-propagating anti-windup algorithm.

First adjustments were done using a model-oriented method, wherein the current loop bandwidth was 2 kHz; PI parameters were acquired on the basis of the electrical constant of an electric motor given by the formula L/R = 1.8 ms.

The gains were then trimmed on the bench using step-response measurements. The most instructive failure was a limit-cycle oscillation that appeared when the integral gain was set too high for the low-inductance motor used in early testing; the oscillation was traced to quantization in the fixed-point integrator, and was resolved by increasing the accumulator width from 20 to 25 bits.

This is the kind of issue that only appears when the algorithm is implemented in hardware, not simulated in floating point.

The SVPWM generator has generated three complementary PWM pairs that operate in a center-aligned mode at 20 kHz. The FPGA determines dead time insertion in the hardware via a programmable counter that shifts the rising edge of each complementary output through a programmable interval (default of 250 ns).

Dead time insertion is a distinct stage in pipeline implementation that occurs after SVPWM comparison, guaranteeing equal application of dead time regardless of the duty cycle.

The PWM outputs were routed to gate drivers with hardware desaturation detection. The FPGA's PWM module included a fault input that, when asserted, immediately forced all six outputs to a high-impedance state within one clock cycle (10 ns). This hardware kill path is a critical safety feature: it does not depend on software response, which would be orders of magnitude slower.

6.1 Shunt-Based Current Sensing

Phase current measurements were made with low-side shunt resistors (1 mΩ, tolerance ±1%, temperature coefficient of 50 ppm/°C) connecting to isolated current sensing amplifiers (gain = 20). The signal from the amplifier was sampled with external 12-bit ADC or 2 MSPS (AD7266), interfaced with FPGA.

The ADC timing was aligned with the midpoint of the PWM cycle, triggered by hardware of the SVPWM control, thereby guaranteeing that the current measured was the average inductor current rather than the peak value of switching ripple.

A published solution for three-phase current synchronous sampling on FPGA notes that continuous current sampling at small time intervals is essential for real-time overcurrent protection, and describes a scheme that incorporates a single set of analog-to-digital converters to enable both synchronous current sampling for motor control and fast timed sampling for overcurrent protection.

The present design used a similar dual-purpose sampling architecture: the control ADC was triggered at PWM center, and a separate high-speed comparator path provided sub-microsecond overcurrent detection.

6.2 Overcurrent Protection Hierarchy

Trustworthiness. Protection was implemented at three levels, with explicitly stated response times:

Level	Mechanism	Response Time	Source
Hardware comparator	Analog comparator on shunt amplifier output → FPGA fault input	< 1 µs	On-board comparator
FPGA internal logic	Current magnitude check in the FOC pipeline	100 ns (one clock)	Verilog
Software monitor	Host processor polls fault registers	1–10 ms	Linux task

An FPGA-based DC motor control patent outlines a dual overcurrent protection mechanism consisting of both an outer protection unit and an inner FPGA logic able to shut the power transistor off using the inner protection signal after a time lag of around 20 µs.

The new version of the design is based on the implementation of the internal checking as a pipelined comparator process, finished within one clock cycle and thus removing the software polling delay of 20 µs completely.

The first prototype showed nuisance tripping during motor speeding up because the threshold value of the hardware comparator was set too close to the maximum ripple current.

The fix was to add a blanking interval of 2 µs after each PWM edge, during which the comparator output was ignored. This is a standard technique in gate-driver design but is easy to overlook when the comparator is external to the FPGA.

In terms of the organization of the control board, it was made with 6 layers of PCB with solid planes serving as ground on layer 2 and as power on layer 5. The FPGA core was inserted in the middle area in addition to four analog-to-digital converters routed via matched length differential pairs so as to provide minimum skew.

In addition, the analog section was divided into 4 isolated areas with the ground islands serving separately in excess of linking it to the main ground through the proper place below the FPGA.

The signals of the gate drive were routed on layer 3 being controlled by 50 Ohm and being matched in length in the range of +/-2 mm for all outputs of each axis and providing necessary performance.

As for the power stage, it implies the usage of 3-phase inverter including IGBT transistors with voltage of 600 V and 30 A current in case of industrial version of 220 V AC as well as operation with DC link of 400 V.

The gate driver was an isolated IGBT driver with desaturation detection and soft turn-off. The DC link capacitor bank was sized at 470 µF per axis to limit voltage ripple to below 5% at rated load.

Authoritativeness. A published FPGA-based high-speed PMSM control system describes a four-layer PCB design integrating power regulation, AD sampling, and encoder reception, with Verilog HDL implementing the core control logic.

The present design adopted a more conservative six-layer stackup because the four-axis architecture required additional routing layers for the isolated gate-drive signals and the differential encoder pairs.

The FPGA made available a register map via the AXI4-Lite to the host processor. The host used the command registers to write the values for current and speed setpoints, and then it read back the position, current, voltage, and fault status information from the telemetry registers.

A DMA channel helped transfer into the host memory the telemetry information at high speeds (current waveforms, position waveforms) without placing any load on the control pipeline.

A literature review of real-time kinematics control systems implemented with the FPGA describes a servo system whereby the current loop is entirely executed in pure hardware logic on the FPGA while the position and speed loops are executed on the host device that makes use of the processed capabilities of the host device in order to guarantee the operation of the communication cycle of outer loops.

The present design followed this partitioned architecture: the FPGA owned the deterministic inner loop, and the host owned motion planning, trajectory generation, and diagnostics.

Parameter	Result	Method
Current-loop period (4 axes)	50 µs	Oscilloscope, PWM sync
Current-loop latency (sample to PWM update)	100 ns	FPGA timing analysis
Encoder position jitter	< 1 LSB at 10,000 RPM	Logic analyzer
Overcurrent trip time (hardware path)	750 ns	Current probe + scope
Position accuracy (BiSS, 17-bit)	± 1 LSB	Reference encoder comparison
Multi-axis synchronization error	< 50 ns	Four-axis step response
Logic utilization (4-axis build)	62% LUTs, 74% DSP48	Vivado report
Power consumption (FPGA core)	1.8 W	On-board sense resistor

We will mention some limitations.

1. The design requires HDL expertise with efficient design and SIM model, firmware changes affecting timing still require re-synthesis, increasing development time.
2. The FPGA has no integrated analog front-end therefore, distilled from ADC and amplifiers family, BOM cost and area of board are increased.
3. The resolver interface was assigned but not populated adding resolver requires additional analog components, which are out of the scope of this build.
4. Logic utilization level of 62% leaves some margin for 2 additional axes but if more than 6 are needed, design must involve another FPGA device.
5. Integration of host processor interface via AXI contributes to the latency until outer loop updates occur; avoiding this problem could have been possible only with a more integrated Zynq SoC solution.

The performance specification of the FPGA-based servo platform was fulfilled by it there were four independent axes, a 50 µs current-loop period, protections shorter than a microsecond in hardware, as well as compatibility with incremental encoders and absolute encoders.

However, the most interesting lessons came from the malfunctions encountered with the help of the simulating dynamometer in the course of testing the servo platform the oscillation of a fixed-point integrator, nuisance trips of a comparator, as well as the necessity to implement protocols of encoders in FPGA fabric right at the beginning of designing with Verilog.

That evidence-driven discipline, combined with a documented trade study and an honest accounting of limitations, is what makes this design defensible and transferable to other high-performance motion-control applications.